`timescale 1ns / 1ps

module Mux (
  input  [1:0]  sel,
  input  [63:0] a,
  input  [63:0] b,
  input  [63:0] c,
  input  [63:0] d,
  output [63:0] result
);
reg [63:0] res;
assign result = res;

always @(*) begin
    case(sel)
        2'b00:   res = a;
        2'b01:   res = b;
        2'b10:   res = c;
        2'b11:   res = d;
    endcase
end

endmodule